Light emitting diodes (LEDs) have been widely used in electronic devices and applications, such as LED display panels. An LED display panel usually comprises an LED array and a LED control circuit that controls the LED array to display images. In a scan-type LED display, the LEDs in the LED array are arranged into rows and columns. In the LED array, a group of LEDs (e.g., arranged in a row or a column) can be coupled to a scan switch that turns the group of LEDs on and off. The group of LEDs is often referred to as a scan line. Another group LEDs can be coupled to a power source. The group of LEDs powered by the same power source is referred to as a channel. An LED simultaneously belongs to a scan line and a channel and emits light when the scan line it belongs to is on.
Furthermore, in an array of RGB LEDs (e.g. 16 columns×8 rows), each R, G, B LED may be powered by a different power source. Accordingly, there are a total of 48 channels to drive 16 columns of RGB LEDs. Each row of the LEDs is coupled to a switch, i.e., a scan line. The eight switches are turned on and off in a sequential manner, lighting up one row of LEDs at a time.
Used herein, the term “couple,” “couples,” “connect,” or “connects” means either an indirect or direct electrical connection unless otherwise noted. Thus, if a first device couples or connects to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices or connections.
One parameter of an LED display is its gray scale value, which is the number of levels of brightness the display can show. The gray scale value equals 2number_of_control_bit. For example, a 16-bit resolution LED display has a gray scale value of 216=65536, which means that the display can exhibit 65,536 level of brightness for each color. Accordingly, a RGB LED has 655363 different color combinations. As such, a frame (i.e., an image) of a RGB LED display may display up to 655363 colors.
Another parameter for an LED is the PWM value, which is the level of brightness of an LED is displaying. In a 16-bit resolution LED display, the PWM value ranges from 0 (complete darkness or black) to 65535 (maximum brightness or white). When the PWM value is low, it means that the brightness level of an LED is low. LED displays often experience performance issues at low PWM values.
Scrambled-PWM (S-PWM) is an enhanced version of PWM that enables a high visual refresh rate. S-PWM scrambles the “on” time in a PWM cycle into several shorter “on” periods and sequentially drives each scan line for a shorter “on” period. In other words, a total PWM value is scrambled into a number of PWM periods (i.e., segments) across a data frame. A data frame means data used to display a frame. In a conventional PWM scheme, there may be only one PWM pulse so that the LED emits light for a continuous time period, leaving the LED unlit for a long period of time. In contrast, S-PWM allows the LED to emit light in consecutive short pulses evenly across the data frame. By doing so, S-PWM increases the visual refresh rate. FIG. 1 illustrates an example of S-PWM, in which a data frame is divided into 32 segments and a PWM pulse is distributed among the 32 segments.
A further parameter for an LED display is its GCLK (i.e., Gray Scale Clock) frequency, which is related to the maximum number of GCLK cycles in a data frame and the refresh rate of the display. The frame rate is the number of times a video source can feed an entire frame of new data to a display in one second. The refresh rate of a LED display is the number of times per second the LED display draws the data. The refresh rate equals the frame rate multiplied by the number of segments.
The control-bit resolution for consumer electronics applications is usually 8 bits. For an 8-bit PWM resolution, there are 256 different gray scale levels. The corresponding PWM period has 256 clock cycles. For a typical 32 KHZ consumer-electronics clock frequency, a PWM period lasts 8 ms=256/32 KHZ. Accordingly, the PWM refresh rate is 125 HZ=⅛ ms. At 8-bit PWM resolution and 125 HZ refresh rate, the display provides sufficient gray scale adjustment and flicker elimination. However, in a 16-bit resolution display with a 2 KHz refresh rate, the GCLK frequency is 2000×65,536=131.072 MHz. Such high clock frequencies pose challenges to CMOS interface and LED driver's output ports.
As an alternative, the 16-bit control data can be divided among MSB (Most Significant Bit) and LSB (Least Significant Bit) for the emulation, wherebyNumber_of_Segments=2BIT_NUMBER_OF_LSB andWidth_of_One_Segments=2BIT_NUMBER_OF_MSB Accordingly, the total width of one data frame is2(BIT_NUMBER_OF_MSB+BIT_NUMBER_OF_LSB)=216=65,536 GCLK cycles
Adopting the S-PWM scheme, assuming a 16-bit resolution display with 11 bits of MSB data, 5 bits of LSB data, a scan number of 8, and a frame rate of 60 Hz, the refresh rate is 1920 Hz, but the GCLK frequency is significantly lower, as shown below.GCLK frequency=216×60 Hz×8=31.45 MHzRefresh rate=60 Hz×2BIT_NUMBER_OF_LSB=60 Hz×32=1920 Hz
Furthermore, the PWM value can be expressed as follows:PWM value=MSBd*2BIT_NUMBER_OF_LSB+LSBdwhereby MSBd stands for the MSB data and LSBd stands for the LSB data. The MSB data is displayed in every segment in the data frame while LSB data is placed into segments when the LSB data are available. In other words, the LSB data determines whether the last GCLK cycle in each segment should be on or off, while the MSB data determines the number of the rest of GCLK cycles. In this approach, the MSB data is the same for all the segments.
For example, when the MSB data is 00000000011 and the LSB data is 00010, the MSB data of 3 is displayed in all 32 segments, while LSB data of 2 is divided into two with one data put into Segment 0 and Segment 31. That is Segment 0 and Segment 31 has (3+1) GCLK cycles and Segments 1-30 each has 3 GCLK cycles. The total PWM value is 98, i.e., 3×32+2=98. If the MSB data is 00000000100 and the LSB data is 00011, each segment displays the MSB data of 4 while the LSB data of 3 is distributed into three segments, e.g., Segments 0, 30, and 31. The total PWM value is 131, i.e., 4×32+3=131.
According to a conventional S-PWM scheme, the MSB data is displayed in every segment in the data frame. A look up table is implemented to allocate the LSB data in the segments. The LSB data for each channel is handled with dedicated memory and look up table. In other words, each channel requires its own dedicated LSB circuit. Using such conventional S-PWM to drive a number of channels poses problems, including large overhead, large chip area, and high power consumption. Accordingly there exists a need for devices and methods that overcome these shortcomings.
SUMMARY OF INVENTION
The current disclosure provides an LED display control circuit. The control circuit has a device configured to separate a first PWM data into LSB data and MSB data. The control circuit also comprises a LSB circuit coupled to a plurality of LED channels. The LSB circuit is configured to supply LSB data to each of the plurality of LED channels sequentially.
To do so, the LSB circuit is coupled to a plurality of latches, each of the latch is associated with one of the plurality of LED channels. The latches are configured to block or to release the LSB data to their corresponding LED channels. The latches are turned on and off so that LSB data is released to the plurality of LED channels. Furthermore, the LSB data released from the latch is combined with the MSB data to generate a second PWM signal. The second PWM signal is outputted to the each of the LED channels.
The current disclosure also provides a method for controlling a scan-type LED display. A control circuit is coupled to the scan-type LED display that has scan lines and channels. The control circuit separates a first PWM data into MSB data and LSB data; and outputs the LSB data into a LSB circuit. The LSB circuit is coupled a plurality of LED channels. The LSB circuit is configured to supply LSB data to each of the plurality of LED channels sequentially. To do so, the LSB circuit is coupled to a plurality of latches, each of the latch is associated with one of the plurality of LED channels. The latches are configured to block or to release the LSB data to their corresponding LED channels. The latches are turned on and off so that LSB data is released to each of the plurality of LED channels.
In one embodiment, the LSB circuit comprises a static random-access memory (SRAM) unit implemented to store LSB data for all channels and scan lines a look up table, such as ROM, electrically connected to the static random-access memory, a multiplexer (MUX) electronically connected to the read-only memory and a plurality of PWM channels electronically connected to the multiplexer. Each channel further corresponds to a shift register for storing data, a latch for controlling the data flow, and a MSB data storage unit.
In another embodiment, the control circuit further comprises a first pipeline register electronically connected to the SRAM and the look up table for temporarily storing data, a second pipeline register electronically connected to the look up table and the multiplexer for temporarily storing data.